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abi.go
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abi_test.go
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all_test.go
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arena.go
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asm_386.s
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asm_amd64.s
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asm_arm.s
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asm_arm64.s
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asm_loong64.s
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asm_mips64x.s
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asm_mipsx.s
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asm_ppc64x.s
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asm_riscv64.s
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asm_s390x.s
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asm_wasm.s
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benchmark_test.go
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deepequal.go
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example_test.go
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export_test.go
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float32reg_generic.go
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float32reg_ppc64x.s
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float32reg_riscv64.s
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internal
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makefunc.go
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nih_test.go
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set_test.go
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stubs_ppc64x.go
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stubs_riscv64.go
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swapper.go
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tostring_test.go
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type.go
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type_test.go
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value.go
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visiblefields.go
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visiblefields_test.go
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Editing: float32reg_riscv64.s
// Copyright 2022 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. #include "textflag.h" // riscv64 allows 32-bit floats to live in the bottom // part of the register, it expects them to be NaN-boxed. // These functions are needed to ensure correct conversions // on riscv64. // Convert float32->uint64 TEXT ·archFloat32ToReg(SB),NOSPLIT,$0-16 MOVF val+0(FP), F1 MOVD F1, ret+8(FP) RET // Convert uint64->float32 TEXT ·archFloat32FromReg(SB),NOSPLIT,$0-12 // Normally a float64->float32 conversion // would need rounding, but riscv64 store valid // float32 in the lower 32 bits, thus we only need to // unboxed the NaN-box by store a float32. MOVD reg+0(FP), F1 MOVF F1, ret+8(FP) RET
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